Using the ElectricTM VLSI Design System

| Steven M. Rubin |
July 14, 2004
Version 7.00

# Table of Contents

Chapter I: INTRODUCTION 1: Welcome 2: Requirements 3: UNIX Installation 4: Macintosh Installation 5: Windows Installation 6: Fundamental Concepts 7: The Display 8: The Mouse 9: The Keyboard 10: IC Layout Example 11: Schematics Example | Chapter II: BASIC EDITING 1: Selection 2: Circuit Creation 3: Circuit Deletion 4: Circuit Modification 5: Changing Size 6: Changing Orientation
Chapter III: HIERARCHY 1: Cells 2: Creating and Deleting Cells 3: Creating Instances 4: Examining Instances 5: Moving Up and Down the Hierarchy 6: Exports 7: Cell Information 8: Rearranging Hierarchy 9: Libraries 10: Copying Between Libraries 11: Cell Views 12: Automatic View Generation | Chapter IV: THE DISPLAY 1: Introduction to the Display 2: The Messages Window 3: Creating and Deleting Editing Windows 4: Scaling and Panning 5: Layer Visibility 6: Colors 7: Grids and Alignment 8: The Component Menu 9: Hardcopy 10: Text Windows 11: 3D Display
Chapter V: WIRE PROPERTIES 1: Introduction to Arcs 2: Constraints 3: Setting Constraints 4: Other Arc Properties 5: Default Arc Properties | Chapter VI: ADVANCED EDITING 1: Making Copies 2: Creation Defaults 3: Options 4: Making Arrays 5: Spreading Circuitry 6: Replacing Circuitry 7: Undo Control 8: Text 9: Networks 10: Outline Editing 11: Project Management 12: Emergencies
Chapter VII: DESIGN ENVIRONMENTS 1: Technologies 2: Units 3: I/O Specifications 4: The MOS Technologies 5: The MOSIS CMOS Technology 6: The Schematic Technology 7: The Artwork Technology 8: The FPGA Technology 9: The Generic Technology | Chapter VIII: CREATING NEW ENVIRONMENTS 1: Introduction to Technology Editing 2: Converting between Technologies and Libraries 3: Hierarchies of Technology Libraries 4: Miscellaneous Information 5: The Layer Cells 6: Special Layer Information 7: The Arc Cells 8: The Node Cells 9: How Technology Changes Affect Existing Libraries 10: Examples of Use
Chapter IX: TOOLS 1: Introduction to Tools 2: Design-Rule Checking 3: Electrical-Rule Checking 4: Simulation 5: Routing 6: Network Consistency Checking (NCC, or LVS) 7: PLA and ROM Generation 8: Pad Frame Generation 9: Silicon Compiler 10: VHDL Compiler 11: Compaction 12: Logical Effort | Chapter X: SIMULATION 1: Introduction to Simulation 2: Simulator Operation 3: VHDL Interface (ALS) 4: Behavioral Models (ALS) 5: Simulation Concepts (ALS) 6: The Gate Entity (ALS) 7: The Function Entity (ALS) 8: The Model Entity (ALS) 9: Documenting the Netlist (ALS)
Chapter XI: LANGUAGE INTERPRETERS 1: Introduction to Interpreters 2: The Lisp Interface 3: The TCL Interface 4: The Java Interface 5: Interpreter Attributes | Chapter XII: MENU SUMMARY 1: The File Menu 2: The Edit Menu 3: The Cells Menu 4: The Arc Menu 5: The Export Menu 6: The View Menu 7: The Windows Menu 8: The Info Menu 9: The Technology Menu 10: The Tools Menu

Copyright (c) 2004 Static Free Software .

ElectricTM is a trademark of Static Free Software .

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