****library: "tsmc25"
version: 5.6.2
aids: 12
aidname: user
aidname: io
aidname: compaction
aidname: pla
aidname: routing
aidname: silicon-compiler
variables: 14
SC_vert_arc[015,01500]: mocmossub:Metal-2
SC_port_x_min_dist[01,01500]: 600
SC_num_rows[01,01500]: 5
SC_active_dist[01,01500]: 600
SC_feedthru_size[01,01500]: 1200
SC_pwell_offset[01,01500]: 0
SC_min_spacing[01,01500]: 600
SC_via_size[01,01500]: 1200
SC_pwell_size[01,01500]: 0
SC_main_pwr_width[01,01500]: 3000
SC_pwr_width[01,01500]: 2100
SC_l2_width[01,01500]: 600
SC_horiz_arc[015,01500]: mocmossub:Metal-1
SC_l1_width[01,01500]: 600
aidname: vhdl-compiler
aidname: compensation
aidname: logeffort
aidname: network
aidname: drc
aidname: simulation
userbits: 3
techcount: 15
techname: generic lambda: 2000
techname: nmos lambda: 4000
techname: cmos lambda: 4000
techname: mocmos lambda: 2000
techname: mocmossub lambda: 300
variables: 1
IO_gds_layer_numbers[042201,01500]: [16,18,28,31,13,-1,11,12,8,-1,2,-1,15,40,17,27,29,52,-1,-1,7,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,62]
techname: mocmos2 lambda: 2000
techname: bicmos lambda: 2000
techname: rcmos lambda: 2000
techname: cmosdodn lambda: 2000
techname: bipolar lambda: 4000
techname: schematic lambda: 4000
techname: pcb lambda: 2540000
techname: artwork lambda: 2000
techname: gem lambda: 2000
techname: efido lambda: 20000
view: schematic-page-1{p1}
view: layout{lay}
view: schematic{sch}
view: icon{ic}
view: documentation{doc}
view: compensated{comp}
view: skeleton{sk}
view: Verilog{ver}
view: VHDL{vhdl}
view: netlist{net}
view: netlist-als-format{net-als}
view: netlist-quisc-format{net-quisc}
view: netlist-silos-format{net-silos}
view: netlist-rsim-format{net-rsim}
view: netlist-netlisp-format{net-netlisp}
view: simulation-snapshot{sim}
view: unknown{}
cellcount: 0
variables: 1
LIB_save_options[01,01500]: 32770
